CMOS (complementary metal oxide semiconductor) circuits are widely used in many applications such as, for example, battery-powered devices such as portable computers and cellular telephones. CMOS is a very effective device configuration for implementation of digital functions due to very low power consumption and dissipation as well minimization of the current in the “off” state.
In implementation, CMOS semiconductors comprise both n-channel and p-channel MOS field effect transistors (MOSFETs), i.e., use both n-channel MOSFETs, and p-channel MOSFETs. However, in CMOS structures, parasitic current paths exists associated by so-called parasitic bipolar transistors, which, under normal conditions, are not activated. CMOS latchup can occur when the parasitic bipolar transistors are activated. Activation can be initiated by voltage or current perturbations, or ionizing radiation. CMOS latchup occurs when regenerative feedback occurs between the npn and pnp parasitic bipolar transistors. Latchup can lead to destructive failure of the semiconductor chip. The latch-up problem will adversely affect the CMOS device and more particularly will degrade its performance.
Various CMOS designs have been conceived to prevent the latch-up problem. For example, it is known to increase the spacing between devices which, in turn, increases the effective base width of the parasitic transistors. As should be understood, with such a design, the bi-polar current will decrease as the base width increases. Thus, in such a design, as the N-diffusion moves away from the N-well, or the P-diffusion moves away from the N-well edge, or vertically, CMOS latch-up is less likely to occur.
Another approach to reducing CMOS latchup sensitivity has been to increase doping concentrations. For example, by increasing the doping concentrations, the minority carrier lifetime is decreased; when the doping is in the base region, the bipolar current gain decreases. In a further design, isolation structures have been provided to prevent the latch-up. For example, isolation structures can be placed deeper than the junctions in which case current cannot flow laterally. In other techniques, “parasitic” collectors can be provided as a current “sink”.
As technology scales, however, the spacing between the P+ diffusion and the N-well and the N+ diffusion and N-well spacing become smaller. Thus, due to the scaling, previous techniques to prevent latch-up are becoming more problematic. For example, it is more difficult to increase the doping in specific areas, since the increase in dopants will increase the out-diffusion of the dopants which, in turn, increases the capacitance of the device (at the junctions) impacting circuit performance. Also, as for isolation structures, as P+ to N+ space is scaled to maintain the aspect ratio of the isolation; hence the isolation structure becomes shallower every generation, not deeper.